1. Field of the Invention
The present invention relates to the digital baseband transmission path of the wireless communication equipments, and more precisely to the control of the modulator and/or the gain controller of such equipments, through a digital interface.
2. Description of the Related Art
In certain communication networks, such as GSM (Global System for Mobile communications), it has been proposed to enhance the data rate through new standards, such as the so-called EGPRS standard (Enhanced General Packet Radio Service). For instance the EGPRS standard has introduced in the GSM network a new modulation scheme, named 8PSK (8 Phase Shift Keying), to improve the data rate previously offered by the GMSK (Gaussian Minimum Shift Keying) modulation scheme.
For flexibility purpose of data transmission, the EGPRS standard defines a multi-time slot (or multislot) and multi-mode operation requiring that more than one time slot out of the eight time slots dividing a GSM frame could be used for data transmission with GMSK or 8PSK modulation. So, the EGPRS wireless communication equipments must comprise a modulator able to switch easily from a GMSK modulation scheme to an 8PSK modulation scheme and vice versa in consecutive time slots.
But, as it is known by one skilled in the art, GMSK is a constant envelope modulation scheme which allows the use of a saturated power amplification with high efficiency, while 8PSK is a modulation scheme which delivers a modulated carrier that varies not only in phase but also in amplitude and therefore can not allow the use of a saturated power amplification but for instance a linear one.
So, in multislot operation the modulation scheme changes but also possibly the power amplification mode, which unfortunately introduces interferences between the adjacent channels associated to consecutive time slots.
In order to reduce these interferences it has been proposed to ramp down the transmit power by means of the gain controller of a power amplifier and to change the modulator and/or the power amplification mode during a guard period provided between the consecutive time slots. It is recalled that the guard period is a time interval dedicated to control and/or switching operation without data transmission.
An alternative to this solution has been notably described in the patent document WO 2004/021659. It consists of a joint GMSK/8PSK I/Q modulator adapted to power ramping by means of I/Q signal shaping (where I and Q are respectively in-phase and quadrature components), without changing neither the power amplification mode nor the modulators. This is done by feeding with zeros the joint GMSK/8PSK I/Q modulator, thereby allowing control of the power of the I/Q signals.
If an external power control loop is used it is required that the modulator function be decoupled from the power control loop, or in other words that the ramping of the power amplifier be not determined by the modulator behaviour, but strictly by the power control loop. This stringent condition requires that the modulator output signal has an instantaneous transition between on/off states (data mode versus forced-zero mode) rather than a smooth one. Such transitions require that the modulation switching as well as the gain changes be timed accurately.
An industrial standard has been proposed to standardize the interfaces between the digital baseband processor (or device), the baseband interface (or BAI) and the radiofrequency (RF) device (which is connected to a power amplifier (or PA)).
It is recalled that, for the transmit direction, the digital baseband processor mainly comprises a digital signal processor (DSP) and a controller device (e.g., ARM) interfacing to the BAI, the baseband interface (or BAI) mainly comprises the modulator, a gain controller, a digital to analog converter (or DAC) and a postfilter interfacing to the radiofrequency (RF) device, and the RF device mainly comprises filters, gain stages and mixers. The digital baseband processor (or device), the baseband interface (or BAI), the radiofrequency (RF) device and the power amplifier (or PA) define what is named the transmission path of a wireless communication equipments.
The digital baseband processor, the BAI and the RF device may be defined on a same chip, or on separate chips, and any combination of two of these three devices may be also defined on a same chip. So, they may be connected one to the other in a “chip-to-chip connection mode” or in a “block-to-block connection mode” (when they are integrated on a same chip). But whatever the connection mode they need to be interfaced through a digital interface.
The industrial standard defines a digital interface, named “digital RF interface” and capable of running a protocol named “digRF”, and a control device to facilitate the data transmission between the baseband device and the baseband interface (or BAI). This is done by means of a coding table stored in the control device and establishing a correspondence between symbols for the radiofrequency device and coding values to transmit to this radiofrequency device through the digital interface.
For instance in the case of a GMSK/8PSK I/Q modulators the coding table comprises 16 symbols, two corresponding to data words for feeding the GMSK I/Q modulator, eight corresponding to data words for feeding the 8PSK I/Q modulator, and the last six being reserved for proprietary use.
Some more information about the digital interface, the digRF protocol and the environment thereof may be found at the Internet address “www.digrf.com”, for instance in the document “DigRF, Baseband/RF digital interface specification: Logical, Electrical and timing characteristics”, Version 1.12.